Parent

IBM 5150 Motherboard:  RAM Refresh

NOTE:

The following is basic, for basic educational purposes.

Background: RAM chip addressing

The dynamic RAM chips used in the IBM 5150 do not store bytes; they store bits.  The bits are in the form of a matrix, a certain number of rows and a certain number of columns.  For example, the 4116 RAM chip stores 16,384 bits, in a cell (bit) matrix that has 128 rows and 128 columns.

To address a particular bit:
1. The bit's row number is presented to the RAM chip's address pins, along with pulsing the chip's RAS pin; then
2. The bit's column number is presented to the RAM chip's address pins, along with pulsing the chip's CAS pin.

See here for a fictional example where the cell matrix is only 8 rows by 8 columns (64 bits).


What does each RAM chip require for refresh ?

Dynamic RAM chips need to be periodically refreshed, and that is done on a row basis, and can be done by simply accessing any bit in the row to be refreshed.

The maker of the chip specifies the minimum required refreshing frequency.  For example, the 4116 dynamic RAM chip has 128 rows, and according to specification, all of the rows need to be refreshed within 2 ms.

The refresh of a row can also be done simply by presenting the row number to the address pins of the RAM chip, and then pulsing the chip's RAS pin.  That is known as 'RAS only refresh' and that is what is done by the 5150 motherboard's RAM refreshing circuitry.


Motherboard's RAM refreshing circuitry

Part of the Timer chip (8253A) is used, and part of DMA controller chip (8237A) is used, and many other chips on the motherboard play a part.

Channel 1 of the Timer chip's three channels (counters) is dedicated to RAM refresh.
Channel 0 of the DMA controller chip's four channels is dedicated to RAM refresh.

During the power-on self test (POST):
•  The POST zeroes the page register used by DMA channel 0.     (See step 3 of here.)
•  The POST sets up timer channel 1 to send a pulse to channel 0 of the DMA chip every approximately 15 μs.     (See step 9 of here.)
•  The POST sets up DMA channel 0 to: Single transfer mode / Address increment / Auto-init / Read transfer / Word count of FFFF hex (65535)     (See here.)

What that results in is:

DMA channel 0's {current word count register} set to FFFF hex (65535) and {current address register} set to 0.

Then, every time that DMA channel 0 receives a pulse from the Timer chip (which is about every 15 μs), the following happens:
Step 1: Certain 5150 motherboard circuitry waits for the 8088 CPU to indicate that it has released control of the address and data buses.
Step 2: The contents of DMA channel 0's {current address register} is put onto the motherboard's address bus.
Step 3: Certain 5150 motherboard circuitry asserts the RAS pin on all of the motherboard's RAM chips.
Step 4: The DMA controller increments its {current address register} for channel 0.  (Channel 0 was configured for 'Address increment')
Step 5: The DMA controller decrements its {current word count register} for channel 0.
Step 6: If that {current word count register} is now -1 (FFFF hex), reinitialise DMA channel 0's {current word count register} to FFFF hex (65535) and {current address register} to 0.

So, if you were to monitor the motherboard's address bus, inspecting its contents every time that DMA channel 0 was 'active' (which is about every 15 μs), you would see an incrementing address:

Active occurrence #1:		Address 0
Active occurrence #2:		Address 1
Active occurrence #3:		Address 2
. . .
. . .
Active occurrence #65536:		Address 65535  (FFFF hex)
Active occurrence #65537:		Address 0	<------------------ reset back to 0
Active occurrence #65538:		Address 1
Active occurrence #65539:		Address 2
. . .
. . .

That is 16 address bits of counting (bits A0-A15), with the address being incremented every 15 μs.  I have seen that for myself using a logic analyser.

And, every time that DMA channel 0 is 'active', you will see the RAS pin of all motherboard RAM chips being pulsed.



What else is happening ?

Various DMA related signals on the motherboard are generated.  They are not important to this 'basic' explanation of RAM refresh.


What do the 5150 motherboard's RAM chips see during refresh ?

The important thing to understand is that the RAM chips on the 5150 motherboard do not 'see' all of the motherboard's address bus.
- In normal operation, they are presented with a row address (row number) with RAS signal, followed by a column address (column number) with CAS signal.
- For the dedicated RAM refreshing mechanism, they are only presented with a row address and a RAS signal (i.e. 'RAS only refresh').

Let us look at the 16KB-64KB version of IBM 5150 motherboard as an example, a motherboard that uses 4116 type dynamic RAM chips.

The 4116 RAM chip is presented with a 7-bit row address followed by a 7-bit column address.
For the dedicated RAM refreshing mechanism, we are only concerned with the presented row address (refreshing is done on a row basis).
On the 5150 motherboard, the 7-bit row address presented to every 4116 chip corresponds to the lowest 7 bits of the motherboard's address bus.

So even though the motherboard's dedicated RAM refreshing mechanism is address counting using 16 bits, i.e. from 0 to 65535 (0000 to FFFF hex), the 4116's row address is created from only the lowest 7 bits of that.

Refresh address		Refresh address
(DMA channel 0)		(a row address)
on address bus		seen by every 4116 chip
--------------------		--------------------------------

0		0
1		1
2		2
3		3
...		...
...		...
127		127
128		0		<-------  4116 chip sees 0  (lowest 7 bits of address 128)
129		1		<-------  4116 chip sees 1  (lowest 7 bits of address 129)
130		2		<-------  4116 chip sees 2  (lowest 7 bits of address 130)
...		...
...		...
...		...
...		...
...		...
65535		127
0		0		<-------  DMA chip reached the final word count programmed for channel 0, resetting the address register back to 0
1		1
2		2
3		3
...		...
...		...

So, from the perspective of a 4116 RAM chip, all of its 128 rows are getting refreshed every 128 x 15 μs = 1.92 ms

Note that the refresh of a row is usually referred to as a 'refresh cycle'.

It was stated before that every time that DMA channel 0 is 'active' (i.e. a refresh cycle), the RAS pin of all motherboard RAM chips is pulsed.  So, for example, row 53 is being refreshed at the same time on all of the motherboard's 4116 RAM chips.


'Dummy' DMA transfer

If you read a description of DMA, DMA is more than simply placing addresses on the data bus: simply put, a block of bytes are being 'copied' by the DMA controller from one location to another.

Is that what channel 0 of the DMA controller is doing in support of RAM refresh?

No.  That is alluded to by the "dummy DMA transfer" that appears in IBM's technical reference for the IBM 5150 when the reference refers to RAM refresh.

Channel 0 is programed by the POST for 'Read transfer' mode.  In that mode, the 8237A DMA controller reads from memory and writes to I/O by:
1. Placing an address on the address bus.
2. Asserting the motherboard's MEMR and IOW signals simultaneously.  (The 8237A is a type of DMA controller that does not store copied bytes within itself.)

That, by itself, suggests that during RAM refresh, a read from address 0 will also write to I/O port 0, a read from address 1 will also write to I/O port 1, a read from address 2 will also write to I/O port 2, and so on.  If writes to low-numbered I/O ports were allowed to occur during RAM refresh, it would 'corrupt' the programmed configuration of various chips on the motherboard, and affect some expansion cards.  If the 5150's motherboard circuit diagram is examined, it is seen that during DMA operations, writes to I/O ports are effectively negated by preventing the 'chip select' lines of the subject chips being asserted.  As for expansion cards, the IBM Game Control Adapter is an example; the use of the AEN signal being used to prevent the subject write to port 201h.

In addition to that, during RAM refresh, CAS signals for motherboard RAM are not generated.

Therefore, functionally, from a motherboard perspective, all that is happening during RAM refresh (i.e. channel 0 of the DMA controller is active), is that an address is put onto the address bus, and the RAS pin of all RAM chips is asserted.


Dynamic RAM on expansion cards

The refreshing circuitry on the motherboard supports refreshing of dynamic RAM on ISA expansion cards.  The designer of the card needs to add some circuitry to the card for that.  An example is at here.

But what if the dynamic RAM chips on the card have more rows than the RAM chips on the motherboard ?

Not a problem. The card is seeing channel 0 of the motherboards DMA controller counting from address 0 to 65535.

For example, let us assume that 41256 RAM chips of '256cycle/4ms' refresh are being used on the card. (256 rows [i.e. 8 bits], which need be refreshed within 4 ms)

Refresh address		Refresh address
(DMA channel 0)		(a row address)
on address bus		seen by every 41256 chip
--------------------		--------------------------------

0		0
1		1
2		2
3		3
...		...
...		...
255		255
256		0		<-------  41256 chip sees 0  (lowest 8 bits of address 256)
257		1		<-------  41256 chip sees 1  (lowest 8 bits of address 257)
258		2		<-------  41256 chip sees 2  (lowest 8 bits of address 258)
...		...
...		...
...		...
...		...
...		...
65535		255
0		0		<-------  DMA chip reached the final word count programmed for channel 0, resetting the address register back to 0
1		1
2		2
3		3
...		...
...		...

So, from the perspective of a 41256 RAM chip of '256cycle/4ms' refresh, all of its 256 rows are getting refreshed every 256 x 15 μs = 3.84 ms



IBM 5150 motherboard's RAM refreshing circuitry

Shown at here and here.  That provides some more detail as to what is going on.


Request versus execution

The pulse generated by Timer channel 1 can be thought of as a 'request for a RAM refresh cycle'.  No actual refresh cycle can then happen until the CPU has relinquished control of the address bus, and the CPU determines when that is.

So, using an oscilloscope, it you were to use the oscilloscope's channel 1 to monitor the Timer channel 1 pulse, and use the oscilloscope's channel 2 to monitor the /DACK0 pulse out of the DMA controller, you would see that the period between the two pulses is continuously varying.


Rectangular cell matrices

Earlier, the following examples were given:
•  The fictional dynamic RAM chip at here, a chip that contains a cell matrix of 8 rows by 8 columns, i.e. a square cell matrix.
•  A 4116 type dynamic RAM chip, a chip that contains a cell matrix of 128 rows by 128 columns, i.e. a square cell matrix.

A square shaped matrix makes sense, because the bit size of the row address and column address presented to a dynamic RAM chip is always the same.
E.g. For the 4116 type chip, both the row and column addresses presented to it are 7 bits wide, corresponding to 128 rows and 128 columns.

However, the data sheets of some dynamic RAM chips show a rectangular shaped cell matrix !!!

An example of that is Motorola's MCM6256B chip.  A 9-bit row address and a 9-bit column address are presented to it, suggesting a cell matrix of 512 rows by 512 columns.  Instead, the block diagram in the chip's datasheet shows 256 rows by 1024 columns.  And the datasheet indicates '256cycle/4ms' refresh.

What's the story ?

Purpose

Presumably, the chip designers reduced the number of rows, to make their chips compatible with more computers ('computers' is more than PC's and PC clones).  For example, let us pretend that long ago, I designed a computer to run the CP/M operating system.  The dynamic RAM refreshing circuitry to be implemented only counted from row 0 to row 127 (128 rows).  I thought I was going to have to use 4116 type RAM chips (16K-bit, in 128 rows by 128 columns), but then I saw that some of the 4164 type chips (64K-bit) have 128 rows rather than 256.  So I went with the 128-row models of 4164, reducing the 'real estate' required for the system board (fewer RAM chips required).  In the user manual, I specified that only the 128-row ('128cycle/2ms') models of 4164 chip can be used.

How

Basically, a bit from the presented row address is not used in the row selection of the cell matrix, instead being used in the column selection of the cell matrix.

A fictional example, a 64-bit chip, is shown at here.  Square cell matrix on the left; rectangular cell matrix on the right.

The datasheet of the Motorola MCM6256B actually shows the rerouting of the bit - see here.



IBM 5150 motherboard - Bits used for RAM refresh

Motherboard type	Count of address bits presented to motherboard RAM chips	Count of those address bits used for motherboard RAM refresh	Comment
5150 motherboard of type 16KB-64KB	7	7	All 4116 class RAM chips have '128 cycle' (7-bit) refresh
5150 motherboard of type 64KB-256KB	8	7 for 4164 class RAM chips of '128 cycle' refresh 8 for 4164 class RAM chips of '256 cycle' refresh